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ISL8204M, ISL8206M
Reference Circuitry For General
Applications
Note: ISL8204M, ISL8206M has integrated 9.76k Ω resistance into
the module (dividing resistor for top side). The resistance
corresponding to different output voltages is as shown in Table 2:
1. Single Power Supply
Figure 15 shows the ISL8204M, ISL8206M application
schematic for input voltage +5V or +12V. The PVCC pin can
V OUT
TABLE 2. RESISTANCE TO OUTPUT VOLTAGES
0.6V 0.8V 1.05V
1.2V
connect to the input supply directly.
C PVCC
R FB
V OUT
R FB
open
1.5V
6.49k Ω
28.7k Ω
1.8V
4.87k Ω
13k Ω
2.5V
3.09k Ω
9.76k Ω
3.3V
2.16k Ω
PVCC
COMP/EN VIN
ISL8204M, ISL8206M
(+5V/+12V)
V IN
C IN
V OUT
R FB
5V
1.33k Ω
6V
1.07k Ω
FB
PHASE
R FB
R SET-EX
ISET
PGND
VOUT
V OUT
C OUT
Initialization (POR and OCP Sampling)
Figure 17 shows a start-up waveform of ISL8204M, ISL8206M.
The power-on-reset (POR) function continually monitors the bias
voltage at the PVCC pin. Once the rising POR threshold has
FIGURE 15. TYPICAL APPLICATION SCHEMATIC
2. Separated Power Supply
Figure 16 shows the ISL8204M, ISL8206M application
schematic for wide input voltages from +1V to +20V. The
P VCC supply can source +5V/+12V or +6.5V to 14.4V.
exceeded 4V (V PORR nominal), the POR function initiates the
overcurrent protection (OCP) sample and hold operation (while
COMP/EN is ~1V). When the sampling is complete, V OUT begins
the soft-start ramp.
PVCC
(+5V/+12V)
or
P VCC
(+6.5V to 14.4V)
C PVCC
V OUT
PVCC
(+1V to +20V)
~4V
CO M P/EN
VIN
V IN
ISL8204M , ISL8206M
FB
PHASE
C IN
V OUT
COMP/EN
R FB
R SET-EX
ISET
PG ND
VO UT
C OUT
FIGURE 16. WIDE INPUT VOLTAGE APPLICATION SCHEMATIC
FIGURE 17. POR AND SOFT-START OPERATION
Applications Information
The typical ISL8204M, ISL8206M application schematic for input
voltage +5V or +12V is shown in Figure 15. External component
selection is primarily determined by the maximum load current
and input/output voltage.
Programming the Output Voltage
The ISL8204M, ISL8206M has an internal 0.6V ±1.5% reference
voltage. Programming the output voltage requires a dividing
resistor (R FB ). The output voltage can be calculated as shown in
Equation 1:
If the COMP/EN pin is held low during power-up, the initialization
will be delayed until the COMP/EN is released and its voltage
rises above the V ENDIS trip point.
Figure 18 and Figure 19 show a typical power-up sequence in
more detail. The initialization starts at T 0 , when either P VCC rises
above V PORR , or the COMP/EN pin is released (after POR). The
COMP/EN will be pulled up by an internal 20μA current source,
however, the timing will not begin until the COMP/EN exceeds
the V ENDIS trip point (at T 1 ). The external capacitance of the
disabling device, as well as the compensation capacitors, will
determine how quickly the 20μA current source will charge the
V OUT = 0.6 × ? 1 + --------------- ?
R FB
9.76k
? ?
10
(EQ. 1)
COMP/EN pin. With typical values, it should add a small delay
compared to the soft-start times. The COMP/EN will continue to
ramp to ~1V.
FN6999.3
July 26, 2012
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